Summary: This talk will introduce attendees to the challenges involved in achieving high performance multicore synchronization. The tour will begin with fundamental scalability bottlenecks in multicore systems and memory models, and then extend to advanced synchronization techniques involving scalable locking and lock-less synchronization. Expect plenty of hacks and real-world war stories in the fight for vertical scalability. Some of the topics introduced include memory coherence and consistency, memory organization, scalable locking, biased asymmetric synchronization, non-blocking synchronization and safe memory reclamation.
Date: Monday, May 16, 2016
Time: 12:00-1:00 PM Eastern Daylight Time
Note: ACM Membership Required
Samy Al Bahra is the CTO of Backtrace I/O, a New York-based company dedicated to improving debug technologies for today’s complex applications. Prior to Backtrace I/O, he was a principal engineer at AppNexus, where he played a lead role in the architecture and development of many mission-critical components of the ecosystem. His work at AppNexus was instrumental in scaling the system to 18 billion impressions with orders of magnitude in efficiency improvements. Prior to AppNexus, Samy was behind major performance improvements to the core technology at Message Systems. At the George Washington University High Performance Computing Laboratory, he worked on the UPC programming language, heterogeneous computing and multicore synchronization.
Samy Al Bahra serves on the ACM Practitioners Board and is Co-Organizer of the 2016 Applicative Conference, which brings together researchers and practitioners to share the latest technologies and trends in computing. He is also a member of the Applicative Program Committee for the Systems Software Developer track.
Click here to register.