Use Cases of Reconfigurable Computing Architectures for HPC
Authors: Dr. Marie-Christine Sawley (Intel Corporation)
Abstract: Use of reconfigurable execution units (mainly FPGAs) for HPC workloads has seen ups and downs, with the last heyday about a decade ago. Significant advances have been made recently in the field of FPGAs and their system integration: new generations provide highly efficient FP units, and fast cache-coherent interconnects to CPUs were announced. On the SW side, the momentum around OpenCL is lowering the entry barriers. This BOF assembles a distinguished panel of speakers, who will give an up-to-date view of existing proof points, specific potential of current and next-generation reconfigurable computing platforms, and remaining limitations to a wider take-up.
Long Description: The use of reconfigurable execution units in the form of FPGAs has been attracting attention from the HPC community for many years, due to significant potential advantages in energy efficiency, very high I/O bandwidth and customizable, fine-grained parallelism. In addition, certain algorithms can be expressed very efficiently using spatial parallelism, as shown by the old R&D results on systolic computing. The last heyday of FPGA use in HPC was about a decade ago. Until recently however, a number of disadvantages on the HW and SW side, combined with rapid progress in general-purpose CPUs and GPGPUs has precluded their general take-up, and FPGAs have survived in HPC in certain niches mainly around data acquisition, correlation and filtering. On the HW side, the disadvantages were the lack of efficient floating point units, limited amounts of high-speed memory, and a cumbersome, comparatively slow connection to host CPUs via PCI Express. On the SW side, programming in VHDL differs starkly from commonly practiced HPC coding, and the tools ecosystem that could bridge that gap was not mature enough.
Significant advances have been made on both fronts: new generations of FPGAs do contain highly efficient FP units and sometimes even general-purpose processors, and cache-coherent fast interconnects between CPUs and FPGAs have been announced. The momentum around OpenCL is lowering the entry barrier on the SW side. Consequently, a growing number of domains, such as DNA sequencing, seismic data analytics or material science simulations are again looking at running entirely or in part on reconfigurable computing units.
This BOF will assemble a distinguished panel of speakers, who will give an up-to date view of existing proof points, the specific potential of current and next-generation reconfigurable computing platforms and the remaining limitations to the wider take-up of reconfigurable computing in scientific computing.
The planned panel of speakers comprises:
David DONOFRIO, LBL
Niko NEUFELD, CERN LHCb, on high rate data taking and event reconstruction
Mike STRICKLAND; Altera
Georgi GAYDADJIEV, Maxeler and Imperial College
David CARRERA, Barcelona Supercomputing Centre, on genomics workloads
Conference Presentation: pdf
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