SRC05. Transactional Storage Class Memory
Student: Ellis Giles (Rice University)
Supervisor: Peter Varman (Rice University)
Abstract: Emerging Storage Class Memory, or SCM, technologies are promising both byte-addressability and persistence near DRAM speeds operating on the main memory bus. This high-speed, byte-addressable persistence will give rise to new applications, but programmers are faced with a dual edged problem of how to catch spurious cache evictions while atomically grouping stores to manage consistency guarantees in case of failure.
Consistency for byte-addressable persistent data coupled with highly concurrent applications for high performance introduces new challenges. Both Hardware and Software Transactional Memory attempt to solve concurrency challenges but do not address durability. On the other extreme, logging techniques that address durability of data structures in view of failure are not conducive for concurrent high performance applications.
This poster identifies and evaluates areas in both HTM and STM that can be extended to provide durability on Storage Class Memories with little burden on performance. Several approaches are implemented and discussed.
Two-page extended abstract: pdf