107. Evaluating Best and Worst Case Scenarios on Two-Level Memory Systems
Authors: Ryan J. Huber (University of Minnesota)Edgar A. Leon (Lawrence Livermore National Laboratory)
Abstract: To achieve the capacity and bandwidth requirements of an exascale memory system, vendors are employing multiple levels of memory: a small high-bandwidth memory close to the processor and a large but low-bandwidth memory. To leverage the high-bandwidth effectively, application developers could explicitly place data structures in fast memory, but this becomes impractical for large HPC codes.
Our long-term objective is to develop metrics to semi-automatically identify candidate data structures to place in fast memory. In this poster, we quantify upper and lower bounds on the potential performance gain/loss of a two-level memory system. We also show that a data placement policy guided by an experienced application developer may not lead to a significant performance improvement, motivating our future work in this area. Finally, we demonstrate how a single-level memory system can provide meaningful insight on the effect of data placement policies before porting a code to a two-level memory system.
Two-page extended abstract: pdf