109. Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture
Authors: Xi Wang (Texas Tech University)John Leidel (Texas Tech University)Yong Chen (Texas Tech University)
Abstract: The majority of modern microprocessors are architected to utilize multi-level data caches as a primary optimization to reduce the latency and increase the perceived bandwidth from an application. However, applications that exhibit random or non-deterministic memory access patterns often induce a significant number of data cache misses, thus reducing the natural performance benefit from the data cache.
In response to the performance penalties inherently present with non-deterministic applications, we have constructed a unique memory hierarchy within the GoblinCore-64 (GC64) architecture explicitly designed to exploit memory performance from irregular memory access patterns with RISC-V-based core and Hybrid Memory Cube (HMC) devices.
In this work, we present two parallel methodologies and associated implementations for coalescing non-deterministic memory requests into the largest potential HMC request by constructing a binary tree-based memory coalescing model. Cogent test results are also presented to further convince the outstanding efficacy of this concurrent DMC design in GoblinCore-64 architecture.
Two-page extended abstract: pdf