SC16 Salt Lake City, UT

110. A Comparative Power-Performance Analysis of Microarchitecture Effects on Heterogeneous CPU-GPU

Authors: Vijayalakshmi Saravanan (University at Buffalo)Sridhar Ramalingam (University at Buffalo)

Abstract: High-Performance Computing (HPC) users are exploring heterogeneous computing through the integration of CPU-GPUs to maximize the computational throughput. The performance of the processors depends on many micro-architectural parameters such as issue-width, functional units, and pipeline depth. The increasing number of processor cores and depth of instruction pipelines continues to add complexity to task/thread parallelism and the ratio of power/performance. To adequately address these issues and potential benefits and pitfalls that may arise from this heterogeneous processors, it is important to have a deep understanding of application-level and microarchitecture-level demands from CPU-GPU cores. Multi-core CPUs have already been studied thoroughly owing to their larger history in the field. This paper aims to evaluate the scalability of CPU-GPU per stream cores and micro-architectural behavior for parallel applications executing on each core type in heterogeneous CPU-GPU processor simulation. To obtain this, we conduct a set of detailed benchmarks for many-core systems from PARSEC.

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