Next Generation of Co-Processors Emerges: In-Network Computing
Primary Session Leader
Event Type
Birds of a Feather
Accelerators
Architectures
Introductory
Networks
TimeTuesday, November 15th12:15pm - 1:15pm
Location255-EF
DescriptionThe latest revolution in HPC is the move to a co-design architecture, a collaborative effort among industry, academia, and manufacturers to reach exascale performance by taking a holistic system-level approach to fundamental performance improvements. Co-design architecture exploits system efficiency and optimizes performance by creating synergies between the hardware and the software.
Co-design recognizes that the CPU has reached the limits of its scalability and offers an intelligent network as the new “co-processor” to share the responsibility for handling and accelerating application workloads. By placing data-related algorithms on an intelligent network, we can dramatically improve the data center and applications performance.
Co-design recognizes that the CPU has reached the limits of its scalability and offers an intelligent network as the new “co-processor” to share the responsibility for handling and accelerating application workloads. By placing data-related algorithms on an intelligent network, we can dramatically improve the data center and applications performance.
Primary Session Leader
Secondary Session Leaders
