Memory Hierarchies: Exposed!
SessionGPU's
Session ChairPhilip C. Roth
Presenter
Event Type
Exhibitor Forum
Accelerators
Architectures
TimeWednesday, November 16th4pm - 4:30pm
Location155-E
DescriptionThis year, the Intel Xeon Phi x200 (Knights Landing) processor and NVIDIA Tesla P100 (Pascal) GPU both became available, each with an integrated high bandwidth (HBW) memory. There are several programming mechanisms for using HBW memory, ranging from special allocate routines with explicit data copies, to using directives to move data between system and HBW memory, to letting the hardware and system software automatically move pages or cache lines to the HBW memory. Future supercomputers are being designed with nonvolatile RAM, programmed either as a solid-state disk or as another level of the memory hierarchy. The days where a programmer can focus on locality and let the system manage data traffic across the memory hierarchy are vanishing. Here we explore the range of memory system designs and how the characteristics are likely to be exposed, virtualized or hidden in current and future programming models and languages.
Presenter
