Future of Memory Technology for Exascale and Beyond IV
Moderator
Event Type
Panel
Architectures
Exascale
Power
TimeFriday, November 18th8:30am - 10am
Location255-BC
DescriptionMemory technology is essential to building a successful exascale system at reasonable energy. Early analysis, including the DARPA UHPC Exascale Report correctly identified the fundamental technology problem as one of enabling low-energy data movement throughout the system. However, the end of Dennard Scaling and the corresponding impact on Moore’s Law has changed the relationship between the processor and memory system and the nature of the memory wall. The lag in the increase in the number of cores compared to what Moore’s Law would provide has proven a harbinger of the trend toward memory systems performance dominating compute capability. This panel will examine some of the critical exascale questions at SC13, SC14, and SC15, and will continue this discussion.
