DCA: a DRAM-Cache-Aware DRAM Controller
SessionManycore Architectures
Session ChairGeorge Michelogiannakis
Event Type
Paper
Advanced
Architectures
Intermediate
Performance
TimeThursday, November 17th2pm - 2:30pm
Location255-EF
Description3D-stacking technology has enabled the option of embedding a large DRAM onto the processor. Prior studies have proposed using this as a DRAM cache. Since the DRAM cache can be orders of magnitude larger than a conventional SRAM cache, the size of the associated cache tags can also be large. Recent works have proposed storing these tags in the stacked DRAM array itself. However, this increases the complexity, with each DRAM cache request translating into multiple DRAM accesses (tag/data).
In this work, we address how to schedule these DRAM cache accesses. We start by exploring whether or not a conventional DRAM controller will work well. We introduce two potential baseline designs and study their limitations. We then derive a set of design principles that a DRAM cache controller must ideally satisfy. Our DRAM-cache-aware (DCA) DRAM controller, that is based on these principles, consistently improves performance over various DRAM cache organizations.
In this work, we address how to schedule these DRAM cache accesses. We start by exploring whether or not a conventional DRAM controller will work well. We introduce two potential baseline designs and study their limitations. We then derive a set of design principles that a DRAM cache controller must ideally satisfy. Our DRAM-cache-aware (DCA) DRAM controller, that is based on these principles, consistently improves performance over various DRAM cache organizations.
