dCUDA: Hardware Supported Overlap of Computation and Communication
SessionAccelerator Programming Tools
Session ChairIgnacio Laguna
Event Type
Paper
Accelerators
Heterogeneous Systems
Intermediate
OS and Runtime Systems
Programming Systems
TimeWednesday, November 16th4pm - 4:30pm
Location355-D
DescriptionOver the last decade, CUDA and the underlying GPU hardware architecture have continuously gained popularity in various HPC application domains such as climate modeling, computational chemistry, and machine learning. Despite this popularity, we lack a single coherent programming model for GPU clusters. We therefore introduce the dCUDA programming model, which implements device-side remote memory access with target notification. To hide instruction pipeline latencies, CUDA programs over-decompose the problem and over-subscribe the device by running many more threads than there are hardware execution units. Whenever a thread stalls, the hardware scheduler immediately proceeds with the execution of another thread ready for execution. This latency hiding technique is key to making best use of the available hardware resources. With dCUDA, we apply latency hiding at cluster scale to automatically overlap computation and communication. Our benchmarks demonstrate perfect overlap for memory bandwidth-bound tasks and good overlap for compute-bound tasks.
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