108. Designing Accelerators for Data Analytics: A Dynamically Scheduled Architecture
Authors
Event Type
Poster
TimeTuesday, November 15th8:30am - 5pm
LocationLower Lobby Concourse
DescriptionConventional High Level Synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data analytics applications. These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dynamic task parallelism. We introduce a dynamic task scheduling approach to efficiently execute heavily unbalanced workloads, at the opposite of conventional HLS flows that employ execution paradigms based on static scheduling. Our approach is validated by analyzing and synthesizing queries from the Lehigh University Benchmark (LUBM), a well know SPARQL benchmark.
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